ModelSim

##  creates a design library

vlib work

## mapping between a logical library name and a directory by modifying the modelsim.ini file

vmap work work  

## compiles Verilog source code and SystemVerilog extensions into a

## specified working library (or to the work library by default

vlog  -work work tcounter.v 

             

vsim -f sim.f -do sim.do tcounter 

vsim -view counter.wlf 

===============

file: run

===============

vlog -incr  tcounter.v

vsim -f sim.f -do sim.do

===============

file: sim.f

===============

-c

-L  ../resource_library/parts_lib/

-wlf tcounter.wlf

test_counter

===============

file: sim.do

===============

run -all

quit -sim

===============

           

Ref

1. ModelSim User's Manual

2. ModelSim Reference Manual

3. ModelSim Tutorial